1. Field of the Invention
This invention relates to computer systems and, more particularly, to graphics generation subsystems and RAMDAC circuits.
2. Description of the Related Art
In general, computer systems include a CPU, system memory, and a plurality of peripheral devices such as video graphics adapters and serial communications controllers. The memory and peripheral devices are typically coupled to the microprocessor through one or more system buses. In Personal Computers (PCs), these buses are controlled by bridge logic, which is commonly separated into two distinct Integrated Circuits (ICs): the system controller and the peripheral bus controller. The system controller commonly referred to as a northbridge in PC systems, includes such devices as a memory controller and one or more high-speed packet-based bus controllers. The peripheral bus controller commonly referred to as a southbridge in PC systems, includes such devices as a power management subsystem, a serial bus controller and an interrupt controller.
Computer system graphics are typically generated by a graphics processor sometimes referred to as a graphics accelerator. The graphics processor is typically a specialized processor, which creates digital images through the use of graphics software drivers. The drivers interpret high-level commands sent to the graphics processor by the main system CPU. The graphics processor then renders the images using more complex rendering commands, thereby reducing the processing needs of the main CPU. The images are broken up into frames of data that can be individually displayed. The graphics processor then stores the frames in a temporary storage memory known as a frame buffer. The frame buffer may be a standalone video memory connected directly to the graphics processor, or it may be a part of the system memory, which has been allocated for use as a frame buffer, as is the case in a Unified Memory Architecture.
Before the digital frames can be displayed on a Cathode Ray Tube (CRT) display, they must be converted to analog signals. For a color display, the digital frame signals are broken up into the three primary colors: red, green and blue (RGB). A special circuit, referred to as a RAMDAC or Palette DAC, accomplishes the digital-to-analog conversion using a random access memory (RAM) look-up table and a digital-to-analog converter (DAC) for each of the three colors. In many cases, the look-up table stores RGB color values associated with 256 different colors. The digital frame data contains RGB color index values for each pixel. When a specific index in the look-up table is accessed, the corresponding digital RGB color value is written to the DAC for conversion.
Although the RAMDAC provides the analog RGB signals, the CRT also needs timing signals including vertical and horizontal synchronization, which synchronize the frames on the display. The graphics processor generates the display timing. In a typical graphics system where the RAMDAC is part of the graphics processor, the timing signals generated by the graphics processor and the analog RGB signals generated by the RAMDAC are sent directly to the display.
Recently, highly integrated processor chips have been proposed which may integrate a CPU and a graphics processor as well as a memory controller and bridging logic normally associated with the northbridge onto one integrated circuit chip.
There are difficulties involved with manufacturing the RAMDAC on the same integrated circuit chip as a CPU. The analog manufacturing process differs from the process used to manufacture a digital CPU core, and sometimes there are supply voltage differences between the digital and the analog subsections. Additionally, the digital noise generated by a CPU can be difficult to filter from the analog subsection.
Therefore, to overcome these manufacturing issues, RAMDAC circuits have been proposed which are manufactured on separate integrated circuit chips than the CPU and graphics processor. In systems employing such standalone circuits, the graphics processor and the RAMDAC operate in a master and slave configuration, respectively. In this configuration, the graphics processor generates all the CRT timing signals and digital frames. The graphics processor also acts as a direct memory access (DMA) controller by causing retrieval of frame data from the frame buffer and then allowing the data to be available to the RAMDAC. This configuration is also known as a push mode configuration because the graphics processor pushes the data to the RAMDAC.
Increased system CPU speeds have made video capture, editing and display available on a PC. Video data may come from a plurality of sources such as a video camera, a Digital Video Disk (DVD), or TV broadcast. The capture of the video data is normally done at the graphics processor. The graphics processor captures the video data and merges the video frames with the graphics frames from the frame buffer and then sends them to the RAMDAC for display. The merging of the video and graphics, which is generally referred to as overlaying, allows the two to be displayed together. Once the video images are captured and displayed, it may be desirable to edit the combined images. It may also be desirable to store the image being displayed on a storage device such as a hard disk or a digital video cassette recorder (VCR).
The problems outlined above may in large part be solved by a graphics subsystem including a RAMDAC, which is implemented on an integrated circuit chip separate from a graphics processor, for connection to a graphics bus.
In one embodiment, a graphics processor implemented on a first integrated circuit chip is configured to render digital image information in response to graphics commands and to store the digital image information in a memory. The graphics commands may be received, for example, from a main CPU within a computer system associated with the graphics subsystem. A conversion unit is further provided on a second integrated circuit chip, which includes a color mapping unit and a digital-to-analog converter. The color mapping unit may include a RAM look-up table and is configured to convert the digital image information into digital RGB display data. The digital-to-analog converter is coupled to convert the digital RGB display data into one or more analog signals for driving a video display. The graphics subsystem further includes a Direct Memory Access (DMA) controller implemented on the second integrated circuit chip. The DMA controller is configured to generate read requests to retrieve the digital image information stored in the memory and to thereby cause the digital image information to be provided to the conversion unit. The DMA controller is further configured to generate write cycles to cause the digital RGB display data to be written to a designated region of memory. The operating system may then transfer the digital RGB display data from the memory into a storage device such as a hard disk drive.
In another embodiment, the graphics subsystem may include a digital video interface implemented on the second integrated circuit chip. The digital video interface is configured to receive the digital RGB display data from the conversion unit and to provide an encoded digital video output to a digital video output port. The digital video interface is further configured to receive encoded digital video from a digital video input port and to provide decoded digital RGB display data for storage and/or subsequent display.
In an additional embodiment, a video stream interface and a graphics and video combiner unit may be implemented on the second integrated circuit chip. The video stream interface is coupled to a local video input port and is configured to provide video image frame data for storage in a local frame store memory, which is also implemented on the second integrated circuit chip. The graphics and video combiner unit is coupled to the conversion unit and is configured to provide digital image information combined with video image frame data to the conversion unit.
In another embodiment, the graphics subsystem may include a display clock generator unit coupled to a programmable timing control register unit implemented on the second integrated circuit chip. The programmable timing control register unit receives information from the main system CPU. The display clock generator unit is configured to generate display timing signals, such as the horizontal and vertical synchronization signals based on information stored in the programmable timing control register unit.
The graphics subsystem may advantageously overcome manufacturing problems associated with processing the RAMDAC and CPU on the same integrated circuit chips. Additionally, the graphics subsystem may advantageously allow a plurality of video streams to be concurrently displayed with computer graphics on a CRT and to store the display data to such devices as a hard disk or digital video cassette recorder (VCR). The stored images may be edited and redisplayed at a later time or combined with additional computer graphics and video streams.